Beneware Verification Automation
Beneware provides automation software for functional verification of digital silicon IPs. Our patented (pending) methodology for analyzing HDL designs and identifying corner cases allows us to automatically generate the SystemVerilog test bench for the design under test. This cuts down the verification time by estimated 50% and helps to prevent re-spins. Beneware operates in Electronic Design Automation (EDA) market.
Verification Studio 1.0 Released!
Beneware launched a new product that significantly decreases functional verification time.
Verification Studio 1.0 provides maximum automation for functional verification of HDL designs. Instead of manual test writing Beneware’s verification tool generates the SystemVerilog test bench and the test sequences automatically.
Read the press release here.
Verification Studio 1.0 provides maximum automation for functional verification of HDL designs. Instead of manual test writing Beneware’s verification tool generates the SystemVerilog test bench and the test sequences automatically.
Read the press release here.
Beneware at DATE 2010
Beneware took part in the leading european conference on electronic system design: DATE 2010, which was held 8-12 March, 2010 in Dresden, Germany.
http://www.date-conference.com
http://www.date-conference.com
